The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, multilayer interconnects are used to connect various devices (transistors, resistors, capacitors, etc.) to form an IC. In a typical multilayer interconnect structure, conductive lines (e.g., copper wires) are laid in stacked dielectric layers and are connected through vias from one layer to another layer. Copper wires and vias are typically fabricated using single or dual damascene processes. In such processes, an underlying dielectric layer is patterned to form trenches, then the trenches are overfilled with copper, and chemical-mechanical planarization (CMP) is used to remove excessive copper, thereby forming copper wires in the trenches. Subsequently, another dielectric layer is formed over the underlying dielectric layer and the above process is repeated to form vias and upper level copper wires. The multiple dielectric layers are patterned with lithography (or photolithography) processes. Sometimes, overlay errors between lithography processes may result in via misalignment with respect to the target copper wire. A misaligned via may cause accidental bridge (shorting) with a nearby copper wire, creating IC defects; or cause excessive etching of the underlying dielectric layer, creating IC reliability issues. Such via-wire misalignment issues become more problematic as the IC miniaturization continues.